GERMANY AND SPAIN IN THE EU SEMICONDUCTOR RACE: STRATEGIC ALIGNMENT AND GAPS
- José-María Súnico
- 2 days ago
- 16 min read
Updated: 23 hours ago
Executive summary
Europe’s semiconductor ecosystem faces its greatest strategic inflection point since the dawn of the digital age. The pandemic, supply-chain shocks and Russia’s war of aggression against Ukraine have all exposed a structural vulnerability: Europe’s dependence on non-European chip design, manufacturing and packaging for technologies that underpin its economy, security and industrial leadership. From automotive systems to energy infrastructure, telecommunications, defence and healthcare, the European economy increasingly depends on devices designed and fabricated abroad.
The European Commission (EC) via the Chips Act, adopted as Regulation (EU) 2023/1781, defines this challenge explicitly: Europe is strong in research, specialised chemicals, lithography equipment and niche integrated-device manufacturing (notably through ASML, Infineon and STMicroelectronics), but remains weak in large-scale manufacturing, advanced packaging, and the ability to translate RDI excellence into industrial deployment. The Staff Working Document accompanying the Act identifies over fifty potential single points of failure along the global semiconductor value chain (see in the figure below the geopolitical complexity of the microelectronics value chain for a smartphone). Hence, Europe risks remaining a sophisticated but thin participant in a hyper-concentrated global market.
In response, the Chips Act established three strategic pillars originally:
Pillar 1: “Chips for Europe” Initiative. Focus on rebuild design, pilot-lines, innovation capacity.
Pillar 2: A Framework for First-of-a-Kind Production Facilities. Focus on attracting fabrication and advanced-packaging investment to EU soil.
Pillar 3: A Coordination and Crisis-Response Mechanism. Focus on monitoring supply-chain risks and ensuring coordinated national reactions.
These pillars were then expanded into the following five operational objectives (fully aligned with the five pillars above):
Building up advanced design capacities for integrated semiconductor technologies;
Enhancing existing and developing new advanced pilot lines across the Union to enable development and deployment of cutting-edge semiconductor technologies and next.generation semiconductor technologies;
Building advanced technology and engineering capacities for accelerating the innovative development of cutting-edge quantum chips and associated semiconductor technologies;
Establishing a network of competence centres across the Union by enhancing existing or creating new facilities;
Undertaking activities, to be described collectively as ‘Chips Fund’ activities, to facilitate access to debt financing and equity, including by providing clear guidance, in particular for start-ups, scale-ups, SMEs and small mid-caps in the semiconductor value chain, through a blending facility under the InvestEU Fund and via de European Innovation Council.
Within Europe, each Member State is expected to specialise and align their national initiatives. Germany and Spain illustrate two distinct yet potentially complementary paths. Germany acts from a position of strength, consolidating an already dense microelectronics ecosystem that holds about 30% of EU wafer capacity. Spain acts from a position of emergence, seeking to catalyse new capacity and attract strategic investment through the PERTE Chip launched in 2022. Both align with the three pillars and five operational objectives of the European Chips Act but differ in scope, governance, and realism.
Germany’s Microelectronics Strategy (2025) focuses on six action fields: expanding chip-design capabilities, accelerating “lab-to-fab” transfer, developing a skilled workforce, incentivising investment, and deepening European and international cooperation. It explicitly adopts a learning (adaptive) governance model and seeks to make the country the EU’s most attractive and skill-rich site for advanced packaging and leading-edge fabrication (see Fig. 3).
Spain’s PERTE Chip positions itself as a catalytic national programme leveraging up to €12.25 billion of Recovery Plan resources to strengthen every stage of the value chain—from open-architecture design (RISC-V), integrated photonics and quantum-related chips, to a nationwide network of cleanrooms and pilot lines (see Fig. 4). Its ambition to explore sub-5 nm fabrication remains aspirational, but its focus on open hardware, photonics and system integration aligns well with Europe’s longer-term innovation agenda.
This report argues that both strategies respond coherently to the EU-level diagnosis but exhibit different strengths and weaknesses. Germany’s plan is pragmatic, incremental and ecosystem-driven; Spain’s is visionary, catalytic and institution-building. The challenge for Europe is to synchronise these efforts (and many others) under a single monitoring and coordination framework, ensuring complementarity rather than duplication, particularly in areas such as advanced packaging, skills development and open-hardware design.
1 Context and European framework: the EU Chips Act and the common challenge
The COVID-19 pandemic paralysed production lines worldwide. Europe’s automotive sector—its industrial backbone—was forced to halt assembly plants because of a lack of microcontrollers worth less than €10 per unit. The subsequent energy crisis, intensified by Russia’s invasion of Ukraine, made this technological dependency a matter not only of competitiveness but also of sovereignty. In advanced economies, semiconductors are now recognised as critical infrastructure—akin to energy, transport or food supply.
Fig. 1 above, and Fig. 2 below, illustrate the complexity of the semiconductor value chain. In the production of a smartphone (see Fig. 1), dozens of countries contribute discrete technologies (e.g., design software, wafers, equipment, chemicals, test and packaging), however, value creation is highly concentrated in East Asia and the United States. The chain for wireless and video-processing chips (see Fig. 2) shows even stronger concentration, with design dominated by US firms and advanced packaging clustered in Taiwan, South Korea and, increasingly, China. Despite Europe’s participation being significant in upstream RDI and equipment supply, it is minimal and continuously decreasing, when it comes to volume manufacturing.
The Chips Act Staff Working Document quantifies the risk:
Over 75% of global manufacturing capacity for logic chips below 10nm lies in 2 countries, and over 70 % of global OSAT (outsourced assembly, test and packaging) capacity resides in East Asia.
Europe’s market share of global semiconductor manufacturing has fallen from 24% in 2000 to around 8% today. Without targeted intervention, it would decline further by 2030.
Structural weaknesses and mechanisms devised to mitigate them
The EC’s diagnosis goes beyond capacity numbers. It identifies four structural weaknesses:
Fragmented innovation and limited scale-up mechanisms. European research is world-class, yet the continent lacks the pilot-line infrastructure and investment vehicles to turn prototypes into production.
Insufficient industrial investment and high entry costs. The capital expenditure for a leading-edge fab exceeds €10 billion. No single Member State—let alone a single firm—can justify such an investment without coordinated public support.
Shortage of specialised skills. Across Europe, universities produce fewer semiconductor engineers than required, and the workforce ages rapidly.
Dependence on foreign supply and limited crisis-response capacity. The 2021–23 chip shortage revealed that Member States acted independently, competing for scarce supply rather than coordinating at EU level.
To counter this situation, the Chips Act aims to double Europe’s global market share to 20% by 2030, attract first-of-a-kind fabs, and establish a monitoring mechanism capable of anticipating supply disruptions. It does so through three complementary pillars:
Pillar 1: “Chips for Europe” initiative.
This pillar focuses on strengthening Europe’s design and innovation capabilities. It proposes the creation of a virtual design platform, competence centres, and several pilot lines covering advanced nodes, heterogeneous integration and quantum or photonic devices. The objective is to provide European researchers and SMEs with the resources they need and currently lack: accessible, affordable and open infrastructures where ideas can be tested and scaled.
Germany and Spain anchor parts of their national strategies in this pillar. Germany links it to the Forschungsfabrik Mikroelektronik Deutschland (FMD) network and its advanced-packaging roadmap. Spain translates it into a network of national cleanrooms and photonics pilot facilities under PERTE Chip’s 8th line of action.
Pillar 2: First-of-a-Kind Production Facilities
Recognising that Europe cannot rely solely on design excellence, the second pillar creates a regulatory and financial framework for large-scale investment in fabs, packaging and testing plants. It allows “Integrated Production Facilities” and “Open EU Foundries” to receive targeted public support—provided they are first-of-a-kind in the Union and contribute to resilience. The aim is to make such projects bankable while preserving competition.
Germany interprets this pillar as a continuation of the Important Projects of Common European Interest (IPCEI) model, using national incentives to attract leading-edge fabrication and advanced-packaging lines to its territory. Spain treats it as a vehicle to explore, after a viability phase, the potential establishment of sub-5 nm fabrication capacity (see PERTE Actuación 8, pp. 26–27). Both rely on the European Commission’s flexible state-aid framework to proceed.
Pillar 3: Coordination and Crisis-Response Mechanism
This pillar seeks to prevent a repetition of the chaotic 2021–22 scramble for chips. It establishes the European Semiconductor Board (ESB), composed of Member State representatives and the EC, to monitor supply-chain indicators, coordinate emergency measures and ensure consistent application of the Regulation. It can trigger a “crisis stage” allowing temporary prioritisation of critical sectors.
Germany’s strategy plans to create a national “Chips Office” that would feed into this mechanism, ensuring continuous learning and data flow. Spain, for its part, has examined changes to national security legislation to enable prioritisation of semiconductor supply during emergencies—a precursor to integration with the EU-wide system.
The European Chips Act is not just a subsidy framework, but a new governance model combining industrial policy, RDI coordination and crisis preparedness. Its success depends on its capacity to align EU-level and national instruments. Without alignment, Europe risks falling into over-centralisation (which would restrain national initiatives) or fragmentation (which would replicate past failures).
The envisioned expected outcomes by 2030 are:
At least two leading-edge fabrication sites established in the EU.
Fully operational pilot lines for advanced, heterogeneous and photonic integration.
A network of competence centres linked to universities and SMEs.
A functioning early-warning and crisis-response mechanism.
A skilled European workforce sufficient to sustain the projected 20% global share.
The position of Member States within this framework
Within this EU architecture, Member States have considerable flexibility. They can design national programmes that emphasise their comparative advantages, provided these contribute to European resilience. Three broad categories have emerged:
Industrial consolidators, such as Germany and France, which already host strong semiconductor clusters and aim to expand them.
Emergent developers, such as Spain or Italy, seeking to enter the ecosystem through targeted investments in design, photonics or pilot facilities.
Specialised enablers, such as the Netherlands (equipment), Austria (power electronics) and Ireland (assembly and test).
Germany and Spain represent the first two categories respectively. In the table below we can see the difference in their strategies, which provides insight into how different Member States interpret the same EU mandate (and the challenge of coordinating 27+1 different strategies).
Tab. 1. Key differences in Germany and Spain starting points
This asymmetry in their starting points explains the difference in tone. Germany’s approach is consolidative and risk-managed; Spain’s is aspirational and capacity-building. Both, however, recognise the need to align with the EU’s pillars and to contribute tangible assets to the ESB’s monitoring network.
A common European challenge.
Ultimately, Europe’s semiconductor race is not a contest between Member States but a test of collective capacity to act strategically. The European Chips Act provides the legal and financial scaffolding, but its real value lies in the coordination it demands. The question is whether national strategies—however well designed—can be synchronised in practice.
The German and Spanish cases will serve as an early test. The continent’s challenge is threefold:
To convert R&D excellence into industrial scale.
To mobilise investment without distorting the single market.
To maintain unity of purpose amid diverse national ambitions.
If Europe succeeds, it will not only strengthen its industrial base but also redefine the governance model for its next generation of strategic technologies. If it fails, it risks repeating the fragmented trajectory of previous industrial initiatives, watching the semiconductor value chain continue to consolidate elsewhere.
2 Germany's microelectronics strategy (2025)
Germany’s Mikroelektronik-Strategie der Bundesregierung (2025) starts from the premise that the country already constitutes Europe’s industrial semiconductor hub. It accounts for roughly 30% of EU wafer capacity and houses strong user industries — automotive, machinery, energy and medical-technology — all of which suffered acute shortages during 2021-23. The strategy’s objective is to strengthen sovereignty and competitiveness by ensuring that Germany can design, manufacture and package critical chips within Europe. The figure below shows the big picture envisioned.
As seen in the figure above, the plan organises its implementation through six areas of action:
Expand chip-design capabilities. Strengthen national design ecosystem and access to EDA-tools.
Accelerate “from lab to fab” transference. Focus on advanced-packaging pilot lines and industrialisation paths.
Grow a skilled workforce base. Expand university capacity and vocational pathways.
Upskill their talent base. Integrate semiconductor-specific curricula and lifelong learning.
Incentivise investment. Deploy IPCEI and Chips-Act Pillar 2 mechanisms for large projects.
Boost EU and global cooperation. Ensure German programmes remain embedded in EU and allied frameworks.
Execution is shared between the Federal Ministries for Economic Affairs and Climate Action (BMWK) and Education and Research (BMBF) through a National Chips Office. This body coordinates funding, monitors metrics and represents Germany in the European Semiconductor Board. The strategy is explicitly described as lernend (learning): iterative, evidence-based and open to adjustment as technological or geopolitical conditions evolve.
The German strategy’s strength lies in its integration of existing assets:
Forschungsfabrik Mikroelektronik Deutschland (FMD). Provides the lab-to-fab interface.
Fraunhofer institutes and universities. Provide a dense R&D base.
Industrial champions. Big industry leaders such as Infineon, Bosch or GlobalFoundries Dresden, anchor demand and private investment.
Germany’s plan is realistic and internally coherent. It focuses on domains where the country is already competitive and avoids over-extension. However, there are still some challenges:
Sub-federal coordination. Success depends on Länder and regional clusters; the federal strategy still lacks binding instruments to align them.
Talent bottleneck. Even with expanded education programmes, Germany faces a global shortage of process and packaging engineers.
Cross-border duplication. Without strong EU synchronisation, national incentives could compete for identical investors and equipment.
Overall, the German approach represents a disciplined, ecosystemic, adaptative, industry-focused consolidation strategy.
3 Spain’s PERTE Chip (2022)
Spain’s PERTE Chip, approved in 2022, positions the country as an emerging actor seeking to create an investable semiconductor ecosystem from near zero. Funded through the Recovery and Resilience Facility, it mobilises up to €12.25 billion across the value chain.
Its philosophy is catalytic rather than consolidative: to leverage public funds to attract private investment, link research to industry and insert Spain into Europe’s semiconductor map.
As seen in the figure above, PERTE Chip defines five main strategic axes:
RISC-V processors and open hardware. Reduce dependency on proprietary architectures dominated by non-EU companies.
Integrated photonics. Exploit Europe’s still-competitive position and Spain’s active research clusters to develop TRL 1-4 capabilities and pilot production.
Quantum and specialised chips. Align with the EU Quantum Flagship to strengthen national computing infrastructure.
Clean-room and pilot-line network. Provide shared national facilities for research, prototyping and small-series fabrication.
Support to strategic sectors. Ensure pull-effect from automotive, industrial equipment, telecommunications, avionics, defence and space industries.
Initially led by a Special Commissioner for the PERTE Chip, the programme sought to centralise coordination among ministries and regions. Funds are channelled through Spain’s public-investment instruments and complemented by venture initiatives for start-ups and scale-ups (11th line of action).
Delays in disbursement and changes in political leadership have weakened this centralised model and presently there seems to prevail tacticism and opportunism over strategy, probably because of the pressure on the deadline to execute the funds (July, 2026).
Spain’s ambition to explore a sub-5 nm fab (8th line of action) signals a will to enter high-end manufacturing but remains technically and financially unproven. Given the time horizon and capital intensity, a more realistic path lies in photonics, heterogeneous integration and advanced packaging — areas where Spain could achieve TRL 6-8 within the decade.
The PERTE’s strength lies in ecosystem activation: connecting research, entrepreneurship and end-user industries. Its weakness lies in execution and focus: overly broad scope, limited talent base and bureaucratic inertia.
Spain’s plan is aspirational and nation-building. It captures the political opportunity of the Recovery Plan but risks dilution without prioritisation and continuity. Nonetheless, its alignment with open architectures, photonics and system integration makes it strategically complementary to Germany’s more manufacturing-centred vision.
4 Comparative Analysis
The table below summarises each country perspective on how to contribute to the EU pillars.
Tab. 2. German and Spanish distinct contribution to EU Pillars
Germany’s governance is federal and institutionalised, with permanent ministries and agencies. Spain’s is centralised and project-based, dependent on political continuity. Germany opts for a learning process — incremental adaptation through monitoring. Spain initially aimed for central control but now faces fragmentation. The German model offers stability; the Spanish model offers agility but at the price of certain degree of volatility.
In summary there is a fundamental difference in their strategic posture:
Germany: Defensive realism. Focus on strengthen existing industrial base, minimise risk, focus on manufacturing competitiveness.
Spain: Offensive experimentation. Diversify technology portfolio, attract new actors, stimulate innovation.
This combination could yield a balanced European portfolio: a set of countries (e.g., France, Germany), could provide the anchor (industrial depth), while others (e.g, Italy, Spain), could act as catalysts (innovation breadth).
In the specific case of Germany and Spain, although promising, we identify a few risks. The table below shows their main strengths and weaknesses.
Tab. 3. Strengths and weaknesses of the German and Spanish strategies
Both countries rely on the Chips Act’s flexible state-aid regime. Unless coordinated by the European Semiconductor Board, incentives may compete for identical private partners, ASML equipment or scarce engineering talent.
The main overall risk is horizontal duplication. Different projects chasing the same niche, rather than vertically overlapping. An EU shared roadmap to align efforts and avoid duplication could transform competition into complementarity. Even more interesting, imho, could be to leave space for controlled potential duplication under a wisely monitored coopetition scheme.
5 Opportunities for synergies and main shortcomings
Both strategies create opportunities for healthy synergies, such as:
Joint open-hardware design platform. Spain’s leadership in RISC-V and Germany’s design-infrastructure strength could converge into a common contribution to the EU’s virtual design platform under Pillar 1.
Advanced-packaging and photonics pilot lines. Germany’s advanced-packaging expertise and Spain’s photonics integration capacities could form a bi-national pilot network, offering Europe end-to-end heterogeneous-integration capability.
Shared skills pipeline. Both recognise human-capital shortages. A joint training programme, co-financed by EU competence centres, could prevent excessive duplication and standardise qualifications.
Crisis-management architecture. Germany’s administrative mechanism and Spain’s legal-priority framework could be merged within the ESB’s Pillar 3 system to create a more operational, industry-aware early-warning network.
Demand aggregation. Neither plan defines clear offtake commitments from domestic industries. A coordinated procurement mechanism for European-made chips — particularly for automotive, defence and telecom sectors — would reinforce investment certainty.
However, in some areas both strategies could be strengthen to avoid shortcomings, such as:
Fragmented demand articulation. Neither strategy quantifies potential domestic demand or establishes procurement targets. Without guaranteed offtake, new fabs and OSAT plants may remain under-utilised.
Limited focus on assembly, test and packaging (ATP/OSAT). The EU SWD identifies this as a major vulnerability. Germany at least references advanced packaging, but Spain gives it minimal emphasis. A coordinated EU ATP/OSAT initiative would address a critical gap.
Temporal misalignment. The PERTE Chip (2022-27) overlaps only partially with Germany’s strategy (to 2029+). Funding windows and investor cycles may diverge. Synchronised calendars under the Chips Joint Undertaking could maximise synergy.
Lack of shared KPIs and monitoring. The EU defines measurable goals (20 % share by 2030, pilot-line milestones, etc.), but national plans lack comparable metrics. A European semiconductor scoreboard would enable transparency and peer learning.
Talent scarcity and mobility barriers. Both countries recognise skill shortages yet rely on national training. Visa facilitation to attact 3rd parties talent and a real EU-wide recognition of technical qualifications are needed to ensure labour mobility.
Governance fragility (Spain) and regional friction (Germany and Spain). Spain’s institutional continuity is uncertain; Germany’s federal complexity and the very fragmented landscape of autonomous communities in Spain may slow coordination. Both will require sustained political commitment beyond electoral cycles.
No clarity on budget beyond July 2026. Considering the strong CAPEX required by this sector, especially when it comes to foundries, clean rooms, and OSAT facilities, and its impact in the decision making by stakeholders in the industry, this lack of clarity might backfire and hurt even the already initiated efforts, as we have already witnessed that big industrial players are not shy when it comes to stepping back. Both strategies will benefit from a more decisive support from their governments and the EU could support them by, e.g., extending the deadline to execute the budget associated to the EU Recovery Plan.
6 Strategic outlook and recommendations
Germany and Spain embody two necessary pillars of Europe’s semiconductor renaissance. Germany provides industrial credibility; Spain contributes innovation dynamism. For Europe to succeed, these must be synchronised within the Chips Act’s governance ecosystem.
Recommendations for Germany.-
Deepen EU integration of pilot-line infrastructure. Ensure that FMD’s advanced-packaging pilots operate as open European facilities.
Adopt measurable performance KPIs on talent development, technology transfer and private investment leverage.
Coordinate Länder actions through binding frameworks to avoid intra-national duplication.
Engage in joint projects with southern-European partners to diversify geography and talent sources.
Recommendations for Spain.-
Prioritise realistic technological niches (photonic and heterogeneous integration, open-architecture design) before pursuing sub-5 nm fabs.
Reinforce governance continuity by institutionalising the PERTE Chip beyond the current political cycle.
Accelerate disbursement of Recovery-Plan funds with transparent selection criteria and performance milestones.
Embed PERTE Chip’s KPIs within EU scoreboards for comparability and credibility.
Joint recommendations.-
Create a DE-ES working group under the European Semiconductor Board to coordinate pilot-lines and skills initiatives.
Establish a common communication strategy highlighting Europe’s collective value proposition to investors.
Pursue a European ATP/OSAT programme combining Ireland experience, German process know-how and Spanish potential sites and potential especialisation in photonics/optronics.
Develop a shared semiconductor-talent visa scheme under the EU Blue Card framework.
The semiconductor race is not merely about technology; it is about Europe’s capacity to act collectively. The German and Spanish cases demonstrate both progress and pitfalls. If managed as complementary vectors within a single European vision, they can anchor a genuinely multi-level strategy where innovation and sovereignty reinforce each other.
If coordination fails, Europe may end up with multiple small projects competing for the same scarce inputs — a familiar “Tower of Babel” pattern. The lesson from past initiatives is clear:
fragmentation kills scale!
7 Conclusions
The comparison of Germany and Spain within the framework of the European Chips Act yields four overarching insights:
Common diagnosis, divergent treatments. Germany consolidates; Spain catalyses. Both respond to the same European imperatives through different lenses of maturity and ambition.
Complementarity or coopetition, over competition. Their respective strengths, Germany’s industrial base and Spain’s innovation drive, can reinforce each other if connected through EU mechanisms, leaving eventually opportunities to coopete in other areas (e.g., CPO packaging which deals with integrating electronics and photonics, seems to be a clear area of interest for both countries).
Governance matters as much as money. Funding volumes are significant but not decisive; execution capacity and institutional stability determine outcomes.
Europe must think as one ecosystem. The Chips Act’s promise will materialise only if national plans feed a single monitoring and crisis-management architecture, supported by transparent KPIs and cross-border pilot networks.
In sum, Germany and Spain represent two sides of the same European coin: resilience through industrial strength, and renewal through innovation. Together, if genuinely aligned, they can transform Europe’s semiconductor dependency into an opportunity for strategic autonomy and sustainable technological leadership.
DISCLAIMER: My views are my own: partial, subjective, biased and, unfortunately, not immune to mistakes nor misunderstandings on my side. In no way I pretend to be accurate in my interpretation, so please, check the original documents and feel free to disagree!
Sources:
PERTE Chip: https://planderecuperacion.gob.es/sites/default/files/2022-05/PERTE_Chip_memoria_24052022.pdf
Mikroelektronik Strategies der Bundesregierung: https://www.bundeswirtschaftsministerium.de/Redaktion/DE/Publikationen/Industrie/mikroelektronik-strategie-der-bundesregierung.pdf
A Chips Act for Europe: https://eur-lex.europa.eu/legal-content/EN/TXT/PDF/?uri=CELEX:32023R1781
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